Integrated circuit technology has progressed to the point where some components of the most technologically sophisticated silicon integrated circuits have dimensions less then one micrometer. As will be readily appreciated by those skilled in the art, dimensions this small permit a relatively large number of devices to be fabricated per unit area on a silicon wafer, and also facilitate fabrication of circuits with a large number of components. Devices are generally electrically contacted through openings, commonly referred to as windows, formed in a dielectric layer overlying a substrate. The term, "substrate," is used to mean material which lies beneath and supports another material. However, as the number of devices increases, the difficulties associated with electrically contacting the devices also increase because of the need to make the electrical contact areas as small as possible and because of the large number of contacts required.
One approach to making electrical contacts at the submicrometer wafer level uses metallizations on several levels with each level of interconnection being on a dielectric, e.g., oxide, layer. However, placing metal interconnections on the dielectric generally requires that the dielectric layer be planarized before the metallization is performed. Thus, this approach simplifies the problem of making electrical connections but creates another problem as will be evident from the following considerations. The windows for the gate contacts and the windows for the source and drain contacts are generally etched through a dielectric layer at the same time. However, the top of the gate is further from the substrate than are the source and drain regions. Thus, the height of the planarized dielectric over the gate is less than is the height of the planarized dielectric over the source and drain regions. The difference in heights may be as much as, for example, 500 nm to 800 nm. Consequently, overetching of the gate occurs in order to etch through the dielectric to the source and drain regions. Moreover, it is critical to open all windows to the source and drain regions, and a slight overetch of the source and drain regions is required to compensate for non-uniformities in the dielectric layer thickness, as well as for non-uniformities in the etching process to ensure opening of all windows. The overetch of the source and drain regions necessarily further overetches the gate windows as well.
However, there is frequently a limit on the permissible overetch of the gate structure. For example, self-aligned silicides, i.e., salicides, are frequently used over polysilicon in the gate structure to, for example, increase electrical conductivity. The salicide is typically approximately 40 nm to 100 nm thick and, to retain the beneficial characteristics of the salicide, no more than fifty percent of it should be removed during the etching process. A typical overetch of the dielectric to ensure opening of the source and drain windows is approximately fifty percent. These three constraints require the window etch to have a selectivity of, at least, approximately 30:1, and preferably 60:1, for the ratio of the dielectric-to-silicide etch. Those skilled in the art will realize that finding an etch having this degree of selectivity represents a formidable task. Of course, generally similar considerations apply if the gate structure is all polysilicon; i.e., a significant overetch of the polysilicon is undesirable.
An alternative to finding such a highly selective etch coats the top of the gate electrode with an insulating, such as nitride, layer. However, this approach is disadvantageous because the nitride-to-oxide etch selectivity is generally not large; e.g., 2:1 to 5:1, and is usually less uniform over the wafer as the selectivity becomes greater. As discussed in the last paragraph, a larger etch selectivity is desirable. Additionally, many phosphorus-doped dielectrics getter contaminants, and the nitride may impair the effectiveness of the getting process.